Flip‑Flops & Sequential Logic — A/L Physics

What must I remember about Flip‑Flops & Sequential Logic?

• Combinational vs Sequential Logic: Combinational logic outputs depend strictly on present inputs (AND, OR, full adders); Sequential logic outputs depend on both present inputs and PAST output history (possesses memory / internal state storage).
• Bistable Multivibrator (Latch / Flip-Flop): Circuit with two stable states (Q = 1, Q̄ = 0 or Q = 0, Q̄ = 1) capable of storing 1 bit of binary information.
• SR Latch (Set-Reset): Built using two cross-coupled NOR or NAND gates: S=1, R=0 => Q=1 (SET); S=0, R=1 => Q=0 (RESET); S=0, R=0 => No Change (HOLD / Memory state); S=1, R=1 => Invalid / Prohibited state (race condition).
• Clocked Flip-Flops: D Flip-Flop (Data latch: eliminates invalid state; Q next = D at clock trigger edge); JK Flip-Flop (universal flip-flop: eliminates invalid state by Toggling Q when J=K=1).

Test yourself (1 minute)

1. Edge-Triggered vs Level-Triggered

   Level-triggered latches respond continuously while clock pulse is HIGH; Edge-triggered flip-flops respond strictly on the instantaneous transition (rising positive edge or falling negative edge) of the clock signal.

2. Frequency Division via T-Flip-Flop

   Connecting JK flip-flop in toggle mode (J = K = 1) divides the clock frequency by 2: f_out = f_clock / 2; cascading N toggle flip-flops yields an N-bit binary ripple counter dividing frequency by 2^N.

3. Shift Registers

   Cascaded chain of D flip-flops sharing a common clock; shifts binary data bit-by-bit sequentially for serial-to-parallel and parallel-to-serial conversion.

Practise Flip‑Flops & Sequential Logic questions today

Source: NIE G.C.E. (A/L) Physics Resource Book - Unit 9: Electronics

What should I study first?

Next in the syllabus

Where does Flip‑Flops & Sequential Logic fit in the syllabus?

Unit 9.8 · Year 2 · Term 2